The present invention relates to digital communication links, and in particular, to a phase detector for providing a mechanism to sense, the phase between the data and the communication link clock signal associated therewith, and most particularly to a phase detector for sensing the dynamic data valid window of the communication link.
To maximize the bandwidth of an interface or a communication link, data is commonly transmitted in a non-retum to zero (NRZ) format. NRZ formatted data only changes logical state when the data changes state. Data is not required to change states on every clock cycle. Consequently, there can be long runs of data without any transitions on the data. Noise, clock jitter and bandwidth limited transmission media can corrupt the data signal transitions.
Typically, the data communicated across the interface or communication link (according to the particular data environment) is captured in the receiving domain using a clock that is synchronous with the transmitting clock. That is, the clock has the same clock rate (baud rate) as the clock in the sending domain. It is desirable to sample the data in the middle of the clock interval. Even if the clock in the receiving domain is phase synchronous with the clock in the sending domain (including accounting for path delays) noise, clock jitter and transmission media affects, as noted herein above, can introduce random, time dependent, skews in the data transmissions relative to the clock in the receiving domain. This is illustrated in FIG. 1 which schematically depicts an xe2x80x9ceyexe2x80x9d diagram as may be used in conjunction with the inventive principles described hereinbelow. Empirically, an eye diagram may be generated for a particular interface or communication link by superimposing multiple random data transitions on top of each other. In FIG. 1, an exemplary eye diagram 100 is shown. Transitions 102 and 104 represent the lower and upper bounds of the setup time error, respectively. The average of these is the average early setup time 106. Similarly, transitions 108 and 110 represent the lower bound hold time error and the upper bound hold time error, respectively. The average late hold time 112 is the mean of these bounds. The center of the eye is functional data 114, the ideal sample point within the error free data valid window 116.
A phase detector may be used in conjunction with a phase locked loop (PLL) or a delay locked loop (DLL) to control the sampling of the data in the receiving domain. The phase detector is used to acquire the phase relationship between the receiving clock and the data. The phase detector output is typically filtered and fed back to control circuits to adjust the phase of the sampling clock, or the data, to reduce the phase error between the two, that is, to optimize the functional data sample point to the center of the data valid region.
Phase detectors typically average the transitions on the data relative to the sampling clock. Analog phase detectors commonly employ a capacitor to hold and accumulate charge proportional to the phase difference between the clock and the data. However, high precision capacitors are difficult to manufacture and must be constantly charged and discharged to function properly. Digital phase detection schemes commonly count edges as a mechanism for averaging the phase detector outputs. However, to average over long periods of time, digital counters must be made large, which dissipates power and consumes area on a chip. Additionally, as discussed hereinabove, NRZ signals may have runs of data without a transition. Therefore, edge counting systems may accumulate significant phase errors before the error is detected.
Consequently, there is a need in the art for a phase detector that has reduced power consumption and reduced sensitivity to NRZ format data. Additionally, there is a need in the art for a phase detector that mitigates these effects without the use of capacitors to average the transitions on the data relative to the sampling clock.
The aforementioned needs are addressed by the present invention. In one embodiment, a phase detector apparatus is provided. The apparatus includes at least one of a first storage unit operable for sampling a first data stream in response to a first clock, and a second storage unit operable for sampling a second data stream in response to a second clock. The second data stream comprises a delayed data stream derived from said first data stream. The apparatus also contains a third storage unit operable for sampling said first data stream in response to said second clock. The first clock comprises a delayed clock derived from said second clock. The apparatus further includes at least one of a first comparison logic and a second comparison logic.
The first comparison logic is operable for receiving a sampled clock signal from said first storage unit and sampled data from said third storage unit. An output of said first comparison logic has a first logic state if said sampled clock data from said first storage unit and sampled data from said third storage unit compare. The output of the first comparison logic has a second logic state if sampled clock signal from said first storage unit and sampled data from said second storage unit miscompare.
The second comparison logic is operable for receiving sampled data from said second storage unit and sampled data from said third storage unit. An output of said second comparison logic has a first logic state if said sampled data from said second storage unit and sampled data from said third storage unit compare. The output has second logic state if sampled data from said second storage unit and sampled data from said third storage unit miscompare.
The foregoing has outlined rather broadly the features and technical advantages of one or more embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.